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g??aoz972gno?^?uf cwy?|?nnpcbbsh7]?s??24\e?r?`%q?' s e r i a l n um be r 2 0 5 0 oz972/OZ976 01/27/04 oz972/OZ976-ds-1.1 page 0 copyright ? 2001-04 by o 2 micro all rights reserved u.s. patent #6,501,234 confidential change summary changes no. applicable section description page(s) 1. ordering information a) add oz972 gn, oz972ign, OZ976 tn & OZ976itn 1 2. oz972 typical application circuit change c18 value from ?0.1u? to ?open? 16 3. throughout data sheet miscellaneous corrections --- revision history revision no. description of change release date 0.97 initial release 10/21/02 0.98 1. revise part number in header and footer to read ?oz972/oz 976? and ensure text diagrams and figures are in this sequence throughout data sheet; 2. add alpha to part numbers in ?ordering information?; 3. add patent number in footer of first page; 4. update the oz972 and OZ976 functional block diagrams, application circuit figures and functional specifications; 5. revise "functional specifications" for oz972 and OZ976 as follows: oz972 - a) first test condition listed, b) add note (2), c) add note (2) to input offset voltage and change max. limit, d) add note (2) to input voltage range, open loop voltage gain and unity gain bandwidth under error amplifier, e) delete power supply rejection parameter, f) add source and sink current parameters [with note (2)] under error amplifier, g) add note (2) to ndr-pdr output resistance (current source) and change max. limit, h) add note (2) to ndr-pdr output resistance (current sink) and change typ. & max. limits, i) change max./min. overlap title to ?maximum overlap?, j) maximum overlap between diagonal switches min. & typ. limits, k) delete gate drive (a,b,c,d) off condition parameter, l) break-before-make pdr_a/ndr_b and pdr_c/ndr_d min. & max. limits, m) ovp test condition, min. and typ. limits; OZ976 - n) add notes (4) & (5), o) add note (4) to reference voltage-nominal and change min., typ. & max. limits, p) add note (5) to reference voltage-line regulation and change max. limit, q) add note (5) to reference voltage-load regulation and change max. limit, r) add source and sink current parameters under reference voltage, s) delete ct oscillator initial accuracy parameter, t) add note (5) to ct oscillator ramp peak and valley and change min. & max. limits, u) ct oscillator clk frequency min., typ. & max limits, v) lct oscillator initial accuracy min., typ. & max limits, w) add note (5) to lct oscillator ramp peak and valley and change min. & max. limits, x) threshold ena min. & max. limits, y) change threshold vin title to ?threshold vin s ? and change min. & max. limits, and z) add talk parameter under threshold; 6. correct subtitle under item ?15.? to read ?vins?; 7. update the formulas for the operation frequency (under item ?16.?) and internal lct frequency (under item ?18.?); and 8. misc. corrections. 04/23/03 0.99 1. features & gen?l description--correct application lamp numbers; 2. correct package type in part name in ordering information; 3. update functional block diagram; 4. update OZ976 typical application circuit; 5. OZ976 pin description--delete note ref. for pin #?s 38, 44 & 45; 6. complete ?package power dissipation? value in absolute max. ratings; 7. oz972 functional specs a) replace ?input voltage range? parameter & limits with ?reference voltage at non-inverting input pin (internal)? parameter & limits, b) correct ?max. overlap between diagonal switches? test condition, c) correct break-before-make ?pdr_a/ndr_b? test conditions, typ & max limits, and ?pdr_c/ndr_d test conditions, min & max limits, d) correct ?ovp? min, typ & max limits, e) correct ?supply current? test conditions, typ & max limits, f) correct ?supply current ? test conditions, typ & max limits, and g) ?sst current? min, typ & max limits; 8. OZ976 functional specs a) add note (5) to ct oscillator ?temp. stability?, and b) correct ?supply current? test conditions; 9. functional description, 7, 6 th line, correct voltage referenced; 10. functional description, 8, 1 st line, correct voltage referenced; 11. functional description, correct voltage referenced in last line; 12. functional description, 18, correct internal lct frequency formula; 13. package information, delete symbol ?c? in table; not included in the drawing; and 14. misc. corrections. 05/13/03 1.0 1 . add oz972ig & OZ976it packages and table that include temp range of each package in ordering information and general descript ion, 2. delete ?i/o? columns in pin description tables, 3. absolute max. ratings a) modify table title, b) move note ?(1)? from ?vdda, vdda2, vddd, vdd? to the table title, c) change ?logic inputs? to read ?signal inputs?, d) revise resonator frequency?, and e) add separate operating temp. table that breaks out commercial and industrial temp ranges, 4. oz972 electrical ch aracteristics revise a) table title, b) add temp range before the table, c) first test condition at beginning of table, d) delete ?input offset voltage? parameter, e) add test conditions and min, typ & max limits for ?reference voltage at non-inverting input pin? and revise current min, typ & max limits, f) delete ?open loop voltage gain? and unity gain bandwidth? parameters, g) change ?source current? title to read ?output voltage?, add symbol and test condition, and revise min, typ, max limits & units , h) delete ?sink current? parameter, i) test conditions for ?ndr-pdr output? parameters, adding min, typ, max limits & units for new test conditions, j) ?break-before-make? parameters min, typ & max limits, k) add test condition plus min, typ, max limits & unit to ?threshold ovp? and update current test conditions, min, typ & max limits, and add ?talk? parameter, l) ?supply current (on)? test conditions, m) ?sst current min, typ & max limits, and n) add ?ctimr current? test conditions, adding min, typ, max limits & units for new test conditions, and revising current min, ty p & max limits, 5. OZ976 electrical characteristics revise a) table title, b) add temp range before the table, c) first test condition at beginning of table, d) add ?nominal voltage? test conditions, adding min, typ, max limits & units for new test conditions, and revising current min, t yp & max limits, e) ?line regulation? note numbers and max limit, f) delete ?load regulation?, ?source current? and ?sink current?, g) add test condition plus min, typ, max limits & unit to ?clk frequency? and update current test conditions, min, typ & max limits, h) add test condition plus min, typ, max limits & unit to ?initial accuracy? and update current test conditions, min, typ & max limits, i) delete ?ramp peak/valley? parameters, j) add note (3) to ?low frequency pwm?, k) add symbol and test conditions (9) plus min, typ, max limits & units to ?duty cycle range? and update current max limit, l) ?threshold? parameter names, deleting ?ena? and vins?, and all limits, m) add note (5) to ?talk? parameter, n) ?supply current (low)? max lilmit, o) ?supply current (high)? test condition and max limit, and p) note (3), 6. oz972 & OZ976 functional block diagrams a) revise ena non-inverting node voltage, sst current, and ovp threshold voltage, and b) delete phase shift in OZ976 diagram, 7 . functional description a) item 7., revise voltage in line 6, b) item 8., revise ovp threshold voltage in line 1, c) item 11., revise non-inverting voltage in last line, and d) item 18., update formula, 8. change c116 value to 33p in OZ976 typical application circuit, 9. add part numbers to titles of package information & 10. misc. free datasheet http://www.datasheetlist.com/
s e r i a l n um be r 2 0 5 0 oz972/OZ976 01/27/04 oz972/OZ976-ds-1.1 page 1 copyright ? 2001-04 by o 2 micro all rights reserved u.s. patent #6,501,234 confidential intelligent ccfl inverter controller features ? low cost synchronized inverter solution ? fixed synchronized operating frequency for up to 48 ccfls ? programmable operating and pwm frequencies ? zero-voltage-switching full bridge topology ? 90% efficiency vs. typical 70% efficiency of conventional designs ? supports up to 12 equal-delay pwm signals ? pwm signals synchronized with either external or internal signal ? intelligent time-sharing dimming control ? constant-frequency design eliminates interference between ccfls and lcd panel. ? built-in intelligence for ignition and normal operation of ccfls ? internal open lamp and over voltage protection ? fewer components and smaller board size ? low stand-by power ordering information part number temp range package oz972g 0 o c to 70 o c 16-pin sop oz972ig -40 o c to 85 o c 16-pin sop oz972gn 0 o c to 70 o c 16-pin sop, leadfree oz972ign -40 o c to 85 o c 16-pin sop, leadfree OZ976t 0 o c to 70 o c 48-pin lqfp OZ976it -40 o c to 85 o c 48-pin lqfp OZ976tn 0 o c to 70 o c 48-pin lqfp, leadfree OZ976itn -40 o c to 85 o c 48-pin lqfp, leadfree general description the phase array (oz972/OZ976) is a unique, high-efficiency, ccfl backlight controller chipset that is targeted for lcd applications requiring 6 to 48 lamps. the phase array chipset consists of two devices, the OZ976 array hub and oz972 power controller. depending on the number of lamps, each application requires one OZ976 device and either 6, 8, 10 or 12 oz972 power drivers. the number of oz972 devices used in an application is user-selectable. figure 1, page 8, illustrates the phase array topology. the oz972, power controller, drives a zero- voltage-switching full-bridge circuit, providing output voltage and current waveforms to the ccfls. operating in a zero-voltage switching configuration; the invert er circuit minimizes emi emission. in addition, the inverter circuit achieves very high power conversion efficiency resulting in lower heat and higher system reliability. a smart protection circuit is incorporated in the power controller to achieve a high safety requirement. this circuit provides lamp ignition, normal operation, open lamp and broken lamp protection, and communicates the status to the OZ976. intelligent open-lamp and over-voltage protection provides design flexibility with various transformer characteristics. the OZ976, array hub, generates and distributes the operating frequency to all oz972 power controllers, to ensure t hat all lamps operate at one frequency. this e liminates interference among lamps that result from different lamp operation frequencies. in terference causes emi problems and may create visual effects (waterfall) on the lcd panel. the operating frequency of the OZ976 is programmable via an external resistor and capacitor. the OZ976 utilizes the pu lse-width-modulation (pwm) dimming method to achieve a wide dimming range. the pwm dimming frequency can be synchronized with an external ttl-level signal or an internal signal, programmed via an internal (lct) oscillator circuit. if an external ttl level signal does not exist, the OZ976 will automatically follow the pre-programmed lct frequency to generate the pwm signals. otherwise, the external ttl level frequency will be used to generate the pwm signals. the OZ976 provides a set of pwm signals with a different phase delay to each oz972. this method reduces power supply ripple. without the pwm phase shift, a system utilizing a large number of lamps, for example 12, would cause a large power supply current surge (spike) if the lamps turned on and off simultaneously. this abrupt power demand increases the power supply design burden and degrades emi performance. by splitting a large power demand into smaller segments, the OZ976 minimizes the peak power bus ripple and in-rush current. the OZ976 monitors the power supply voltage to prevent an under-voltage lockout condition. OZ976 will disable all the inverters if it detects an under-voltage condition. free datasheet http://www.datasheetlist.com/
s e r i a l n um be r 2 0 5 0 oz972/OZ976 confidential oz972/OZ976-ds-1.1 page 2 the oz972 is available in a 16-pin sop package and the OZ976 in a 48-pin lqfp package. both devices are specified over the commercial temperature range from 0 o c to 70 o c, and the industrial temperature from -40 o c to 85 o c. free datasheet http://www.datasheetlist.com/
s e r i a l n um be r 2 0 5 0 oz972/OZ976 confidential oz972/OZ976-ds-1.1 page 3 oz972 pin description name pin no. description vdd 1 ic power ref 2 reference voltage input ct 3 saw tooth wave with double inverter operating frequency clk 4 square wave with inverter operating frequency talk 5 strike/normal/shut down indicator ena 6 enable input; ttl signal ? active high ctimr 7 ccfl ignition period timer sst 8 soft-start timer ovp 9 output voltage sense, vth=2.0v fb 10 ccfl current feedback signal cmp 11 compensation output of the error amplifier gnd 12 ground pdr_c 13 pmosfet drive output ndr_d 14 nmosfet drive output pdr_a 15 pmosfet drive output ndr_b 16 nmosfet drive output OZ976 pin description name pin no. description ena_pp 3 enable oz972 vdda2 4 analog power vdda 5 analog power vddd 6 digital power osca 7 connected to 4mhz resonator oscy 8 connected to 4mhz resonator vsync 9 external synchronization input, ttl signal talk 10 oz972 feedback ignition/normal/abnormal l11 14 low frequency pwm signal with x11 phase delay l10 15 low frequency pwm signal with x10 phase delay l9 16 low frequency pwm signal with x9 phase delay l8 17 low frequency pwm signal with x8 phase delay l7 18 low frequency pwm signal with x7 phase delay l6 19 low frequency pwm signal with x6 phase delay l5 20 low frequency pwm signal with x5 phase delay l4 21 low frequency pwm signal with x4 phase delay l3 22 low frequency pwm signal with x3 phase delay l2 23 low frequency pwm signal with x2 phase delay l1 27 low frequency pwm signal with x1 phase delay l0 28 low frequency pwm signal with no phase delay gndd 29 digital ground gnda 30 analog ground gnda2 31 analog ground ref 32 reference voltage output; 2.5v typical @ 100ua clk 33 inverter operating clock ct 34 timing capacitor set inverter operating frequency pol 38 pol(polarity), select dimming voltage polarity ind 39 ind(individual), select oz972 system protection mode ena 40 enable input; ttl signal rt 41 timing resistor set operating frequency rt1 42 timing resistor for progra mming ignition frequency and pwm frequency lct 43 timing capacitor set internal pwm frequency sel1 44 lamp number selector, work with sel0 sel0 45 lamp number selector, work with sel1 vdim 46 a dc voltage for dimming control vins 47 input voltage sense, vth=1.5v nc 1, 2, 11, 12, 13, 24, 25, 26, 35, 36, 37, 48 no connection free datasheet http://www.datasheetlist.com/
s e r i a l n um be r 2 0 5 0 oz972/OZ976 confidential oz972/OZ976-ds-1.1 page 4 absolute maximum ratings (1) vdda, vdda2, vddd, vdd 7.0v gnda, gnda2, gndd, gnd +/-0.3v signal inputs -0.3v to vdda +0.3v resonator frequency 8mhz oz972 OZ976 package power dissipation 86 o c/w 63 o c/w maximum junction temp. 125 o c storage temp. -55 o c to 150 o c recommended operating range vdda, vdda2, vddd, vdd 4.7v ~ 5.3v inverter operating frequency (2) 30khz to 150khz r t for inverter operating 40k ? to 150k ? resonator frequency selection (3) 3mhz to 4mhz oz972/OZ976 oz972i/OZ976i operating temp. 0 o c to 70 o c -40 o c to 85 o c notes : (1) the ?absolute maximum ratings? are those values bey ond which the safety of the device cannot be guaranteed. the device should not be operated at these limit s. the ?functional specifications? tabl e defines the conditions for actual device operation. exposure to absolute ma ximum rated conditions for extended peri ods may affect device reliability. (2) the frequency of pdr_a, ndr_b, pdr_c, and ndr_d output pulses, f abcd , are half of ct frequency value . (3) see table 2, page 16 for more detail. free datasheet http://www.datasheetlist.com/
s e r i a l n um be r 2 0 5 0 oz972/OZ976 confidential oz972/OZ976-ds-1.1 page 5 oz972 electrical characteristics oz972: 0 o c < tamb < 70 o c, unless otherwise specified oz972i: -40 o c < tamb < 85 o c, unless otherwise specified limits parameter symbol test conditions vdd = 5.0v; ref = 2.5v; unless otherwise specified min typ max unit error amplifier tamb=25 o c 1.26 1.28 1.31 v reference voltage at non- inverting input pin (internal) temp coefficient - 50 - ppm/ o c output voltage (2) v 11 v 10 = 0v; r load =15k 3.0 - - v ndr-pdr output tamb=25 o c; r load =30 ? - 27 33 ? output resistance (2) r p temp coefficient - 3000 - ppm/ o c tamb=25 o c; r load =30 ? - 27 33 ? output resistance (2) r n temp coefficient - 3000 - ppm/ o c maximum overlap max. overlap between diagonal switches clk = 63khz ca=cb=cc=cd=1nf (1) 78 - - % break-before-make pdr_a/ndr_b clk = 63khz ca=cb=cc=cd=1nf (1) 70 115 160 ns pdr_c/ndr_d clk = 63khz ca=cb=cc=cd=1nf (1) 55 105 150 ns threshold tamb=25 o c 2.16 2.22 2.28 v ovp temp coefficient - 500 - ppm/ o c logic high 2.0 - - v talk (2) logic low - - 1.0 v supply supply current i off ena = low - 150 200 a supply current i on ena = high; clk = 63khz - 4.0 5.0 ma sst current i sst 2.5 5.0 7.6 a tamb=25 o c 1.9 2.6 3.3 a ctimr current i ctimr temp coefficient - 4500 - ppm/ o c notes : (1) ca: capacitor from pdr_a (pin 15) to vdda cb: capacitor from ndr_b (pin 16) to ground cc: capacitor from pdr_c (pin 13) to vdda cd: capacitor from ndr_d (pin 14) to ground (2) denotes that parameter is guaranteed by design and not production tested. free datasheet http://www.datasheetlist.com/
s e r i a l n um be r 2 0 5 0 oz972/OZ976 confidential oz972/OZ976-ds-1.1 page 6 OZ976 electrical characteristics OZ976: 0 o c < tamb < 70 o c, unless otherwise specified OZ976i: -40 o c < tamb < 85 o c, unless otherwise specified parameter symbol test conditions limits vdda/vdda2/vddd = 5v; unless otherwise specified min typ max unit reference voltage tamb = 25 o c; i load = 0.25ma 2.39 2.55 2.71 v nominal voltage (4) ref temp coefficient - 200 - ppm/ o c line regulation (2, 4) vdda = 4.7v ? 5.3v - 4 - mv/v ct oscillator tamb = 25 o c; ct = 220pf, rt = 48.7k ? (1) 58 63 68 khz clk frequency temp coefficient - 200 - ppm/ o c lct oscillator tamb = 25 o c; lct = 10nf, rt = 48.7k ? (2) 1 1 9 9 0 0 210 230 hz initial accuracy temp coefficient - -500 - ppm/ o c low frequency pwm (l0-l11) (3) vdim = 1v; pol = 0v; vsync frequency = 70hz; lct = 10nf, rt = 48.7k ? (2) 0 - 0 % vdim = 1.5v; pol = 0v; vsync frequency = 70hz; lct = 10nf, rt = 48.7k ? (2) - 18 - % vdim = 3.2v; pol = 0v; vsync frequency = 70hz; lct = 10nf, rt = 48.7k ? (2) - 70 - % vdim = 1v;pol = 0v; vsync = gnda; lct = 10nf, rt = 48.7k ? (2) 0 - 0 % vdim = 1.5v;pol = 0v; vsync = gnda; lct = 10nf, rt = 48.7k ? (2) - 50 - % vdim = 2.2v;pol = 0v; vsync = gnda; lct = 10nf, rt = 48.7k ? (2) 100 - 100 % vdim 3.2v; pol = 5v; vsync = gnda; lct = 10nf, rt = 48.7k ? (2) 0 - 0 % vdim = 2.5v; pol = 5v; vsync = gnda; lct = 10nf, rt = 48.7k ? (2) - 50 - % duty cycle range l0-l11 vdim 1.8v; pol = 5v; vsync = gnda; lct = 10nf, rt = 48.7k ? (2) 100 - 100 % free datasheet http://www.datasheetlist.com/
s e r i a l n um be r 2 0 5 0 oz972/OZ976 confidential oz972/OZ976-ds-1.1 page 7 OZ976 electrical charac teristics (continued) OZ976: 0 o c < tamb < 70 o c, unless otherwise specified OZ976i: -40 o c < tamb < 85 o c, unless otherwise specified parameter symbol test conditions limits vdda/vdda2/vddd = 5v; unless otherwise specified min typ max unit threshold enable 2.0 - - v disable ena - - 1.0 v vins (on) 1.65 - - v vins (off) - - 1.25 v logic high 3.5 - - talk (5) logic low - - 1.6 v supply supply current ena = low - 165 280 a supply current ena = high 12-phase selection vdim = 2v; l0-l11 = 50k ? (3) clk = 63khz; lct = 210hz - 4.4 5.5 ma notes : (1) ct: capacitor from ct (pin 34) to ground rt: resistor from rt (pin 41) to ground (2) lct: capacitor from lct (pin 43) to ground rt: resistor from rt (pin 41) to ground (3) l0-l11: 50k ? resistor is connected from l0-l11 (pins 14-23 and 27-28) to ground a 4mhz resonator is connected to osca and oscy (4) reference voltage measured when ct, clk, lct & resonator are not active . (5) denotes that parameter is guaranteed by design and not production tested . free datasheet http://www.datasheetlist.com/
s e r i a l n um be r 2 0 5 0 oz972/OZ976 confidential oz972/OZ976-ds-1.1 page 8 phase array topology (1,0) (1,0) (1,0) (1,0) oz972 #1 oz972 #1 oz972 #2 oz972 #2 oz972 #3 oz972 #3 oz972 #4 oz972 #4 oz972 #5 oz972 #5 oz972 #6 oz972 #6 oz972 #7 oz972 #7 oz972 #8 oz972 #8 oz972 #9 oz972 #9 oz972 #10 oz972 #10 oz972 #11 oz972 #11 oz972 #12 oz972 #12 OZ976 array hub and synchronizer ind pol sel0 sel1 e n a _ p p r e f c l k c t talk lpwm l0 ? l11 l0 l4 l1 l2 l3 l5 l8 l6 l7 l9 l10 l11 sel1 0 0 6 0 1 8 1 0 10 1 1 12 sel1 0 0 6 0 1 8 1 0 10 1 1 12 sel1 sel1 0 00 0 6 6 0 0 1 1 8 8 1 1 0 0 10 10 1 1 1 1 12 12 sel0 no. of phases 4 12 figure 1 free datasheet http://www.datasheetlist.com/
s e r i a l n um be r 2 0 5 0 oz972/OZ976 confidential oz972/OZ976-ds-1.1 page 9 functional block diagram description oz972 power controller the functional block diagram of the oz972, power controller, is shown in figure 2, page 10. the reference block receives a reference voltage from the ref pin and generates precise voltages for internal use. the drive circuit consists of four outputs, pdr_a, ndr_b, pdr_c and ndr_d. the drive circuit is designed to achieve a zero- voltage switching full-bridge application. an error amplifier is provided to regulate the ccfl current. the soft-start time (sst) circuit offers a gradual power increase to the ccfl during the ignition period. the soft-start time (sst) is programmable by using an external capacitor coupled with the sst current source. the over-voltage protection block limits the striking voltage for the ccfls. the striking time is programmable by using an external capacitor with the ctimr current source. the protection block intelligently differentiates between lamp ignition, normal operation, open- lamp condition and broken lamp condition. the oz972 communicates its? status to the OZ976 via the open drain talk pin. the oz972 is enabled when the ena circuitry receives an enable signal from the OZ976 (ena_pp). the adj (adjust) control block provides an increased reference voltage during sst and a preset reference voltage once the lamp current is regulated. OZ976 array hub the functional block diagram of the OZ976, array hub, is shown in figure 3, page 11. a precision reference block provides reference voltages for both internal and external use. the ct oscillator circuit generates a user- programmable operating frequency to the oz972?s by utilizing an external capacitor and timing resistor. to select the striking frequency, add an external resistor to rt1. the striking frequency is programmable. the lct oscillator block utilizes a quarter of the current through the timing resistor (rt) to charge and discharge the external capacitor. this creates the lct triangular waveform. the protection block monitors supply voltage, system enable and oz972 status. through vins, the OZ976 monitors the supply voltage and provides under-voltage lock out protection. when vins and ena pins are satisfied, the oz972?s are enabled through the ena_pp pin. when the supply voltage drops belo w specification, the OZ976 disables the inverters. the OZ976 operation is enabled through a ttl signal interface via the ena circuitry. the ind (individual) pin is used to select the system protection mode. when ind is set high, all oz972?s act independent of each other. when ind is set low, all oz972?s act as a group. the talk pin is used to monitor and communicate the status of the oz972 power controllers to the OZ976. a pwm signal is generated when vdim exceeds a threshold voltage. a lct oscillator generates a triangle waveform (1v to 3v) and accepts a vdim dc voltage to generate the pulse width of the pwm dimming signals. the synchronize circuit selects the pwm frequency source from either the internal lct or an external ttl signal to the vsync pin. if an external signal to vsync exists, that signal becomes the pwm frequency source. otherwise, lct is the pwm frequency source. an x2 frequency circuit doubles the pwm source frequency to eliminate low frequency flicker detected by the human eye. the phase delay circuit divides the pwm source period into multiple phases according to the number of lamps used in the application. the user selects the number of phases by selecting the logic levels of pins sel0 and sel1. the pulse width extractor extracts the pwm width from the output of lct comparator. by selecting the pol (polarity) logic level, the designer programs the relationship between vdim and the panel brightness. setting pol high, an increase in vdim, will increase panel brightness. conversely, setting pol low, a decrease in vdim, will increase panel brightness. the pwm generator circuit combines the phase delay, x2 frequency and pulse width information to generate a set of new pwm waveforms with different phase delays. an external resonator, connected to pins oscy and osca, is needed to generate precise frequency and pulse width information to generate the pwm signals l0 to l11. free datasheet http://www.datasheetlist.com/
s e r i a l n um be r 2 0 5 0 oz972/OZ976 confidential oz972/OZ976-ds-1.1 page 10 oz972 power controller fu nctional block diagram vdd ref ct clk talk ena ctimr sst ndr_b pdr_a ndr_d pdr_c gnd cmp fb ovp reference bbm zvs phase-shift control bbm protection adjust control - + - + 5 ua 1.28 v 2.22 v ea control logic figure 2 free datasheet http://www.datasheetlist.com/
s e r i a l n um be r 2 0 5 0 oz972/OZ976 confidential oz972/OZ976-ds-1.1 page 11 OZ976 array hub functional block diagram vdda gnda vins ena talk ena_pp ind vsync sel0 sel1 ref clk ct rt rt1 lct vdim pol vdda2 gnda2 - + - + reference 1.45v ct oscillator uvlo lct oscillator protection synchronization vdda2 gnda2 x2 frequency pulse width extractor pwm generator 1/4 freq vref phase delay 12 vddd gndd oscy osca l0 l11 switch s0 s11 s1 s2 figure 3 free datasheet http://www.datasheetlist.com/
s e r i a l n um be r 2 0 5 0 oz972/OZ976 confidential oz972/OZ976-ds-1.1 page 12 functional description 1. concept the phase array is designed for a multiple-lamp ccfl panel. the OZ976 provides the reference voltage, enable signal, programmable synchron- ized operating frequency and pwm signals to each oz972. in addition, when in common mode, the OZ976 monitors the status of the oz972 via talk. each oz972 operates its own lamps to reach the ultimate performance. this structure minimizes process tolerance and over-head cost while each lamp operates on its designed condition to provide the best performance. 2. oz972 steady-state operation referring to the schematic shown in figure 4, page 17, the oz972 drives a full-bridge power train where the transformer couples the energy from the power supply source to the ccfl. the switches in the bridge denoted as qa, qb, qc and qd are configured such that qa/qb and qc/qd are turned-on complementarily. the turn- on duration of qa/qd and qb/qc simultaneously determines the amount of energy delivered to the transformer and subsequently to the ccfl. the current in the ccfl is sensed and then regulated by adjusting the turn-on time (overlap) for both diagonal switches. this is accomplished through an error amplifier in the current feedback loop. a voltage loop is used to regulate the output voltage to achieve the stri king voltage, which is programmable by using a capacitor divider. over voltage protection (ovp) limits transformer voltage under an open lamp condition. a soft- start circuit ensures a gradual power increase to the lamp. the soft-start capacitor determines the rise rate of the voltage on the sst pin. the voltage level determines the on-time duration (overlap) of diagonal switches qa/qd and qb/qc. the output drives for power mosfet gates include, pdr_a, ndr_b, pdr_c and ndr_d, which output a complementary square pulse. the operation of the four sw itches is implemented with zero-voltage-switching to provide a high- efficiency power conversion. 3. oz972/OZ976 interface signals referring to the schematics in figures 4 and 5, pages 17 and 18, the OZ976 provides a reference voltage, enable signal, clk and ct signals, to each oz972. the OZ976 provides a precise reference voltage to the ref pin of each oz972. all oz972?s are enabled by the OZ976 via the ena_pp pin. the clk and ct signals are used to direct each oz972 to drive qa, qb, qc and qd. all oz972?s are synchronized to one frequency. by sharing the reference voltage, ct and clk, the difference in each lamp?s performance is minimized. the OZ976 controller senses the system power supply voltage. in addition, when in common mode, the OZ976 monitors oz972 operation status via the talk pin to determine whether to maintain normal operation or disable the inverters. once the system is powered-on, the oz972 enters the start-up stage. refer to section 4 for more detailed information. 4. oz972 operation - individual the oz972 operates in a constant-frequency mode. this eliminates any undesired interference between the inverter and lcd panel where interference is usually associated with variable- frequency designs. start- up based on a 4mhz resonator, the OZ976 sends out a reference voltage and approximately 1ms later enables all the oz972?s. clk and ct signals are sent out at this moment. after receiving a reference voltage and enable, clk and ct signals, the oz972 initiates operation. the result is a series of complementary output square pulses from pdr_a, ndr_b, pdr_c and ndr_d. the oz972 holds the talk pin low through an open-drain structure to inform the OZ976 to start the ignition period. soft start time to normal operation an external resistor rt1 provides the flexibility to set a higher operating frequency for ccfl striking. in addition, the striking time is programmable through an external capacitor ctimr. the soft start function gradually increases the energy delivered to the load from the diagonal switches during start-up. during soft start, the talk pin is pulled low requesting the OZ976 to send a higher operating frequency to ignite the lamp. this process continues until the ccfl current is detected and reaches a regulated value. the output of the error amplifier, cmp, follows the feedback signal and controls the overlap of output drives qa/qd and qb/qc to maintain lamp current regulation. the operation of the four sw itches is implemented with zero-voltage switching to provide a high- efficiency power conversion. once the lamp current is sensed and regulated, the oz972 releases talk. when the talk signal is released, the external resistor pulls talk high and communicates to the OZ976 to switch the lamp to a normal operating frequency. the last oz972 and the external pull-up resistor decide the talk level. free datasheet http://www.datasheetlist.com/
s e r i a l n um be r 2 0 5 0 oz972/OZ976 confidential oz972/OZ976-ds-1.1 page 13 soft start time to open lamp the striking voltage, or open-lamp voltage, is regulated through a voltage feedback loop. this voltage feedback loop is monitored by the ovp and controls the overlap of the output drivers to achieve a regulated striking voltage. once the striking time has expired (ctimr) and no lamp current is sensed, the oz972 shuts down and releases talk. the external resistor pulls talk high informing the OZ976 to switch to a normal operating frequency. approx imately 20us later, the open lamp oz972 pulls talk low indicating to the OZ976 that an abnormal condition exists. normal operation to lamp broken a protection feature is needed to disable a damaged lamp during normal operation. once the oz972 senses the missing current signal through the error amplifie r, the protection circuit shuts down the output drives. the oz972 with the broken lamp then pulls talk low informing the OZ976 of an abnormal situation. dimming dimming control of the in verter is implemented by adjusting the amount of energy processed and delivered to the ccfl. a pwm dimming control scheme is internally generated which provides a recommended pwm duty cycle of 0% to 85%. the OZ976 provides the phase delay pwm signals. the pwm frequency source can be provided externally from the system or internally by programming the lct circuit. 5. oz972 operation - group soft-start time to normal operation the oz972s drive the power train to the ccfls after receiving an enable signal. in the soft-start period, talk is pulled low and a striking frequency is provided by the OZ976. each oz972 takes a different time to regulate the ccfl current due to lamp and component tolerances. when the lamp current is regulated on all oz972?s, the talk signal is released. an external resistor pulls talk high informing the OZ976 to provide a normal operating frequency to all lamps. refer to figure 6, page 19. soft-start time and open lamp during the soft start time, an oz972 in open lamp condition attempts to ignite the ccfl. once the striking time has expired and no lamp current is sensed, the oz972 shuts down. by this time, the remaining oz972?s successfully regulate their lamp current and talk is released. the external resistor pulls talk high. the talk rising edge informs the OZ976 to switch all lamps to a normal operating frequency. approx imately 20us later, the oz972 with the open lamp pulls talk low. the OZ976 will check the setting of the ind pin to decide whether to disable all the inverters. refer to figures 7 and 8 on pages 20 and 21, respectively. lamp broken when an oz972 senses no ccfl current in normal operation, its prot ection block shuts down the circuit. the shut down behavior does not affect the operation of the other oz972?s and lamps. the oz972, in shut down condition, pulls talk low and informs the OZ976 of an abnormal condition. the OZ976 will check the setting of the ind pin and decide whether to disable all the inverters. dimming refer to cases 1 and 2 on pages 22 and 23, respectively. after talk goes high and vdim is within the lct signal range of 1v to 3v, the OZ976 pwm generator sends out a set of pwm signals to all the oz972s. the vdim voltage level and lct signal decide the pulse width of the pwm dimming signals. the pwm frequency is decided by the internal lct signal or external vsync signal. each pwm signal has the same pulse width and frequency. each signal has an equal amount of phase delay between them. the delay time is determined by the following equations: case 1: external vsync signal t2 delay time = 2 x number of phases case 2: internal lct signal t1 delay time = 2 x number of phases each oz972 adjusts the power delivered to its corresponding lamp following the pwm signal. this phase shift dimming control method minimizes the ripple current on the power line. 6. protection during the ignition period, open-lamp protection is provided through both ctimr and ovp. this ensures that a rated volt age is achieved and a required timing period is satisfied. removal of the ccfl during normal operation will trigger the error amplifier output and shut down the oz972. free datasheet http://www.datasheetlist.com/
s e r i a l n um be r 2 0 5 0 oz972/OZ976 confidential oz972/OZ976-ds-1.1 page 14 7. ctimr-ccfl ignition time the ignition time varies for ccfls, depending on their length, diameter, module package, manufacturer and temperature. oz972 provides a flexible design where a capacitor is connected to the ctimr pin to set the maximum striking time. when the ovp pin reaches a 2.22v threshold, the ctimr capacitor starts to charge. when the ctimr has expired (ctimr capacitor voltage reaches approximately 3v) and no current is sensed, the oz972 shuts down. an approximation of the timing calculation is: t[second] = c[uf] this capacitor remains reset at no charge if the lamp is connected and in normal operation. 8. ovp the ovp threshold is set at 2.22v nominal. when the output voltage reac hes the threshold, it commands the qa/qd and qb/qc switches to maintain a regulated striking voltage. this ensures that the output has sufficient striking voltage while operating the transformer safely. 9. oz972 ena a logic high ttl signal from the OZ976 to the ena pin of the oz972 enables the power controllers. a logic low signal to the ena pin will disable the operation of the inverter. toggling this signal resumes the operation of the oz972. 10. soft-start time -- sst the soft-start function is provided with a capacitor connected to sst pin. the sst provides a rate of rise for the pulse width where diagonal switches are turned on. this function reduces in-rush current and prevents unnecessary stress to both the ccfl and the transformer. 11. error amplifier ccfl current is regulated through the error amplifier. it also provides the intelligence of differentiating open-lamp striking versus removing the lamp during normal operation. the non-inverting reference is at 1.28v nominal. 12. operating frequency the programmable operating frequency is decided by OZ976. ct and clk signals are necessary for oz972 operation. the oz972 combines the clk, ct and sst or cmp signals to drive the four output drives. 13. output drives the four power mosfet gate output drives are designed so that switches qa/qb and qc/qd never turn on simultaneously. the configuration prevents any shoot-through issue associated with bridge-type power conversion applications. by adjusting the overlap conduction between qa and qd, qb and qc, the ccfl current regulation is achieved. the overlap is adjusted when the power source voltage varies. the four output drive pins provide drive to two p-channel level shifters and two direct gate drive n-channel mosfets. 14. OZ976 operation principle referring to figures 1 (page 8) and 5 (page 18), the OZ976 provides the dc reference voltage, enable signal, synchronized operating frequency, pwm dimming signals and protection services to each oz972. each oz972 provides operating status to the OZ976 through talk. 15. OZ976 protection block vins the OZ976 provides vins to sense the input power supply voltage to the inverter. when under-voltage lock out is triggered, the OZ976 disables the oz972?s through the ena_pp pin. ena a logic high ttl signal to the ena pin enables the operation of the ic. a logic low signal to the ena pin disables the oper ation of the inverter. toggling this signal allows the turn-on and turn- off of the inverter. ind (individual) and talk the ind feature is user programmable. when ind is set high, all oz972s work individually. in this situation, when a lamp is damaged or open, the corresponding oz972 will shut down and pull talk low, indicating to the OZ976 that an abnormal situation exists. the OZ976 will ignore the falling edge of talk and maintain system operation. when ind is set low, all oz972s work as a group. once the OZ976 detects a talk falling edge, the OZ976 pulls ena_pp low to disable all the inverters. refer to figures 7 and 8 on pages 20 and 21, respectively. free datasheet http://www.datasheetlist.com/
s e r i a l n um be r 2 0 5 0 oz972/OZ976 confidential oz972/OZ976-ds-1.1 page 15 ena_pp the OZ976 ena_pp pin connects to all enas of oz972. when vins, ena, ind and talk are satisfied, ena_pp goes high to enable the operation of the oz972s. the system will be disabled when vins is in an under-voltage lock out condition or ena is low. in addition, when talk has a falling edge with ind set low, ena_pp goes low and disables the system. in this condition, only when vins and ena are satisfied, toggling vdda will resume system operation. 16. operation frequency a resistor rt and capacitor ct determine the operating frequency of the OZ976. the frequency is calculated as follows: 675 ? 10 3 c t [pf] ? r t [k ? ] the OZ976 also provides an optional striking frequency if desired. w hen rt1 is used, it is connected in parallel with rt during the ignition period, and provides a higher frequency for striking. after enable, OZ976 detects talk pin?s first rising edge and rt1 is disconnected. ct is a saw-tooth waveform and its frequency is double the f clk operation frequency. clk is a square waveform and its frequency is the operation frequency. both of these signals are used by the oz972 to contro l the output drivers, pdr_a, ndr_b, pdr_c and ndr_d. 17. reference voltage OZ976 is the voltage source providing all oz972 the reference voltage through ref pin. all oz972s follow the ref voltage and generate internal references. the reference voltage is activated approximately 1ms before ena_pp goes high and it lasts 1ms after ena_pp goes low. the time delay relates to the resonator frequency of osca and oscy. 18. pwm dimming control OZ976 provides pwm dimming signals to each oz972 with an equal phase delay. internal lct frequency the internal pre-programmed pwm frequency t1 (see case 2, page 23) is determined by a capacitor connected to the lct pin. an approximation of the frequ ency can be calculated by: 102 ? 10 3 c lct [nf] ? r t [k ? ] the peak and valley of the lct signal is nominally 3v and 1v respectively. the vdim signal is compared to the triangle wave in lct and yields a proper pulse width to modulate the ccfl current. by programming pol, the positive or negative pulse width will be duplicated and imposed on the pwm signal. the designer defines the relationship between vdim and panel brightness. setting pol high, an increase in vdim, will increase the panel brightness. conversely, setting pol low, a decrease in vdim, will increase the panel brightness. pwm frequency through vsync, pwm signals can be synchronized with an external control signal with a ttl level frequency range from 65hz to 180hz. if a vsync signal does not exist, the OZ976 uses the lct signal to synchronize the pwm signals. all pwm signals are synchronized with either the internal (lct) or external (vsync) signal. the pwm signals are twice the frequency of the internal or external signal. pwm dimming signals the pwm dimming signal frequency is extracted from either an internal lct signal or from the external vsync signal. t he pulse width of pwm dimming signal comes from the comparison result of lct and vdim. there is a fixed phase delay between sequential pwm dimming signals. the pwm generator gener ates a new set of pwm dimming signals resulting from the combination of pulse width, x2 pwm dimming frequency and phase delay. all pwm signals have the same pulse width and frequency. the only difference among the pwm signals is the phase delay, which is determined by the pwm dimming period divided by the number of phases. no two pwm signals have the same phase shift amount. sel0 and sel1 the sel0 and sel1 pins are used to select the number of lamps, from 6, 8, 10 and 12. table 1. OZ976 phase select logic sel0 sel1 no. of phases 0 0 6 0 1 8 1 0 10 1 1 12 l0 to l11 l0 to l11 are the pwm signal output pins. all of the outputs are a 3-state buffer. f clk[khz] = f lct [hz] = free datasheet http://www.datasheetlist.com/
s e r i a l n um be r 2 0 5 0 oz972/OZ976 confidential oz972/OZ976-ds-1.1 page 16 19. resonator a 4mhz resonator is used to provide a precise pulse width and frequency to the pwm generator in order to generate the pwm dimming signals. osca and oscy pins are provided to connect a resonator. table 2. resonator frequency selector resonator lct/vsync minimum frequency 4mhz 61hz 3.59mhz 55hz 3mhz 46hz free datasheet http://www.datasheetlist.com/
s e r i a l n um be r 2 0 5 0 oz972/OZ976 confidential oz972/OZ976-ds-1.1 page 17 oz972 typical application circuit figure 4 open free datasheet http://www.datasheetlist.com/
s e r i a l n um be r 2 0 5 0 oz972/OZ976 confidential oz972/OZ976-ds-1.1 page 18 OZ976 typical application circuit input (cn1) & setting notes: 1. vin=18v (16v to 20v) 2. operation freq=56khz 3. lpwm freq=100hz, vp=3.3v to 5v pol=1; 0%: max brightness 38%: min brightness pol=0; 100%; max brightness, 62%; min brightness 4. user can disable panel in all cases -> individual=0 5. number of phases 6 phases : sel0=0, sel1=0 8 phases : sel0=0, sel1=1 10 phases : sel0=1, sel1=0 12 phases : sel0=1, sel1=1 note: input lpwm signal to cn1 pin 11 (lpwm) figure 5 free datasheet http://www.datasheetlist.com/
s e r i a l n um be r 2 0 5 0 oz972/OZ976 confidential oz972/OZ976-ds-1.1 page 19 sst to normal operation time ena _ pp sst talk sst once the oz972's are enabled, all oz972's pull talk low striking frequency normal operation frequency oz972#1 oz972#1 fb sst fb oz972#2 a ll oz972's are in normal operation oz972#2 figure 6 free datasheet http://www.datasheetlist.com/
s e r i a l n um be r 2 0 5 0 oz972/OZ976 confidential oz972/OZ976-ds-1.1 page 20 sst to open lamp- group operation OZ976 ind pin set low time ena_pp sst talk fb sst once the oz972's are enable, all oz972's pull talk low striking frequency sst fb oz972#1 0v ovp ctimr striking all other oz972's are disabled oz972#1 shuts down normal operation frequency oz972#1 oz972#1 oz972#1 oz972#2 oz972#2 ( open lamp ) once the oz972?s are enabled, all oz972?s pull talk low figure 7 free datasheet http://www.datasheetlist.com/
s e r i a l n um be r 2 0 5 0 oz972/OZ976 confidential oz972/OZ976-ds-1.1 page 21 sst to open lamp- individual operation OZ976 ind pin set high time ena_pp sst fb talk once the oz972's are enable, all oz972's pull talk low sst normal operation frequency striking frequency sst fb oz972#1 0v ovp ctimr striking all other oz972's remain in normal operation oz972#1 shuts down oz972#1 oz972#1 oz972#1 oz972#2 oz972#2 ( open lamp ) once the oz972?s are enabled, all oz972?s pull talk low. figure 8 free datasheet http://www.datasheetlist.com/
s e r i a l n um be r 2 0 5 0 oz972/OZ976 confidential oz972/OZ976-ds-1.1 page 22 case 1: external vsync signal 6 lamp application with pol=1 t1 w t1 t2 t1 t2 1/2 t2 w t1 w ww w w 1/2 t2 d www w 1/2 t2 www d w 1/2 t2 www w 1/2 t2 www d d vdim lct comparison result of vdim/ lct external vsync l0 l1 l2 l3 l4 w 1/2 t2 ww d l5 d = 1/2 * t2 * 1/6 free datasheet http://www.datasheetlist.com/
s e r i a l n um be r 2 0 5 0 oz972/OZ976 confidential oz972/OZ976-ds-1.1 page 23 case 2: internal lct signal 6 lamp application with pol=1 t1 w t1 1/2 t1 w w vdim lct comparison result of vdim/ lct l0 l1 w w w d d l2 l3 l4 l5 1/2 t1 w w w 1/2 t1 w w w 1/2 t1 w w w 1/2 t1 w w w 1/2 t1 w w w d d d free datasheet http://www.datasheetlist.com/
s e r i a l n um be r 2 0 5 0 oz972/OZ976 confidential oz972/OZ976-ds-1.1 page 24 package information - 16-pin sop: oz972g power controller a a1 e b d c l inches millimeters dim min max min max a 0.0532 0.0688 1.35 1.75 a1 0.0040 0.0098 0.10 0.25 b 0.013 0.020 0.33 0.51 c 0.0075 0.0098 0.19 0.25 d 0.3859 0.3937 9.80 10.00 e 0.1497 0.1574 3.80 4.00 e 0.050 bcs. 1.27 bcs. h 0.2284 0.2440 5.80 6.20 l 0.016 0.050 0.40 1.27 0 8 0 8 1 h e free datasheet http://www.datasheetlist.com/
s e r i a l n um be r 2 0 5 0 oz972/OZ976 confidential oz972/OZ976-ds-1.1 page 25 package information - 48-pin lqfp: OZ976t array hub d d1 e e1 a e a2 b 1 millimeter inch symbol min. nom. max. min. nom. max. a 1.40 1.50 1.60 0.052 0.059 0.063 a2 1.35 1.40 1.45 0.050 0.055 0.057 b 0.17 0.22 0.27 0.007 0.009 0.011 d1 6.90 7.00 7.10 0.272 0.276 0.280 d 8.90 9.00 9.10 0.350 0.354 0.358 e1 6.90 7.00 7.10 0.272 0.276 0.280 e 8.90 9.00 9.10 0.350 0.354 0.358 e - 0.50 - - 0.020 - free datasheet http://www.datasheetlist.com/
s e r i a l n um be r 2 0 5 0 oz972/OZ976 confidential oz972/OZ976-ds-1.1 page 26 important notice no portion of o 2 micro specifications/datasheets or any of it s subparts may be reproduced in any form, or by any means, without prior written permission from o 2 micro. o 2 micro and its subsidiaries reserve the right to make changes to their datasheets and/or products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. all products are sold subject to the terms and c onditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, patent infringement, and limitation of liability. o 2 micro warrants performance of its products to the spec ifications applicable at the time of sale in accordance with o 2 micro?s standard warranty. testing and other quality control techniques are utilized to the extent o 2 micro deems necessary to support this warranty. specific testing of all parameters of each device is not necessarily performed, except those mandated by government requirements. customer acknowledges that o 2 micro products are not designed, manufactured or intended for incorporation into any systems or products intended for use in connection with life support or other hazardous activities or environments in which the failure of the o 2 micro products could lead to death, bodily injury, or property or environmental damage (?high risk activities?). o 2 micro hereby disclaims all warranties, and o 2 micro will have no liability to customer or any third party, relating to the use of o 2 micro products in connection with any high risk activities. any support, assistance, recommendation or information (collectively, ?support?) that o 2 micro may provide to you (including, without limitation, regarding the desi gn, development or debugging of your circuit board or other application) is provided ?as is.? o 2 micro does not make, and hereby disclaims, any warranties regarding any such support, including, without limitation, any warranties of merchantability or fitness for a particular purpose, and any warranty that such support will be accurate or error free or that your circuit board or other application will be operational or functional. o 2 micro will have no liability to you under any legal theory in connection with your use of or reliance on such support. copyright ? 2004, o 2 micro international limited free datasheet http://www.datasheetlist.com/

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